1. Field of the Invention
The present invention relates to a serial interfacing technique, and more particularly, to a clock recovery apparatus in which a clock embedded in data is recovered by using multiple time masks (windows).
2. Discussion of the Related Art
In the field of flat panel displays (FPD), panel size, the number of pixels, and operating speed have been sharply increased. As a result, the amount of data has also been increased. Therefore, it is necessary to improve the performance at a data receiving end to process the data substantially simultaneously.
A conventional interface, such as multipoint-low voltage differential signaling (m-LVDS) or LVDS, separately transmits the clock and the data. In the serial interface that separately transmits the clock and the data, as the data rate increases, timing skew between the clock and the data may adversely affect correct data transmission.
In recent years, a clock-embedded serial interface that transmits a clock embedded in data has been proposed.
FIG. 1 is a view illustrating a clock recovery structure of a conventional clock-embedded serial interface.
In the clock embedded serial interface of FIG. 1, a transmitting end transmits data having a clock embedded therein, and a receiving end extracts and recovers the clock from the data.
A phase locked loop/delay locked loop (PLL/DLL) 10 generates multi-phase clocks. A mask generator 20 generates a time mask using the multi-phase clocks at a time when a clock is extracted from data. As a result, the clock is accurately recovered by positioning the time mask at the corresponding timing or phase.
Specifically, the mask generator 20 generates the time mask using the multi-phase clocks generated by the PLL/DLL 10, and an AND gate 30 receives the original input data and the time mask generated by the mask generator 20 and recovers the clock.
At this time, the generated time mask is positioned to be synchronized with the clock or the cover a rising edge and a falling edge of the clock, so that the clock is recovered irrespective of a value of the data region.
However, process, voltage, and temperature (PVT) conditions act as considerable variables in clock recovery and can cause severe variations in clock recovery conditions. Therefore, stable clock recovery may not be performed efficiently or correctly.
Specifically, even if the time masks are ideally generated using the multi-phase clocks of the PLL/DLL 10 (which are not independent of PVT conditions), a time delay generated during generation of the time mask can vary depending on the PVT conditions, so that the time mask is not accurately positioned.
When the time delay depending on the PVT conditions is greater than a predetermined setting amount, the recovered clock is output later than the original timing, which increases the amount of jitter of the PLL/DLL 10. Consequently, an error in clock recovery may gradually increase, and therefore, an error rate in data recovery may also gradually increase.
On the other hand, when the time delay is smaller than the predetermined setting amount, the recovered clock may be output earlier than the original timing, which can also increase the amount of jitter of the PLL/DLL 10. Consequently, the clock and the data may not be properly recovered.
For this reason, the position of the time mask should be gradually and/or manually corrected in view of the respective PVT conditions. Therefore, a new apparatus for performing such operations is proposed.